A Current-Mode DTCNN Universal Chip

The paper describes an analog current mode realization of Discrete-Time Cellular Neural Networks (DTCNNs) with high cell density, which have local analog and local logic memory. Hence, some important parts of the CNN Universal Machine concept are implemented. The computation speed can be adjusted simply to the application by changing the clock rate. The circuit components are described in detail and SPICE level 2 simulation results are given for the ORBIT 2.0 pm process. A layout has been designed for a chip with 12 by 12 cells on a square grid realizing a oneneighborhood with 9 feedback and 9 control coefficients. The cell size is 619 pm by 425 pm and the simulated speed is between lMHz and 10MHz depending on the minimum value of the state current. For the latter this leads to a simulated performance of 25.9 lo9 XPS for a single chip operation with an effective area of 0.379 cm2 and a worst case power consumption of 0.86 W. Another important feature of the chip is its capability for a spatial cascaded connection.